Objective

Principal Electrical Engineer with strong experience in hardware architecture, high-speed digital and mixed signal hardware design, design for EMI and ESD, digital signal processing, FPGA and firmware design, as well as mass production in Asia.

Summary of Qualifications

Leadership

Team management, Mentoring, Agile for HW, project estimates
JIRA Agile plug-in

Hardware

Architecture, validation, characterization, design for cost, early cost estimates
High-speed digital design (MIPI CSI-2, USB 3, DDR3, HDMI, LVDS)
post-layout Signal Integrity simulation (Ansys SIwave)
Schematic design, EMI, ESD
Altium, OrCAD/Allegro, PADS, Git, SVN

FPGA

Architecture, Design, Verification, VHDL, Verilog, PSL Assertion Language, SoC, AXI
MicroBlaze, PicoBlaze, Xilinx ISim, Aldec Active-HDL, Modelsim, GHDL, Icarus Verilog

Firmware

Architecture, C/C++, Python, Perl, Assembly, DSP
Git, SVN, GCC

Manufacturing

Cost conscientiousness, Contract Manufacturing in Asia, ECN process
Arena PLM, Eng-DB-2

Other

Altium scripting, LabVIEW, JIRA, MS Office, Confluence, Django webframework programming

Professional Experience

Mar 2026 - present		Principal Electrical Engineer at AIM Intelligent Machines Redmond, WA, USA Moving earth, at scale, autonomously.
Jan 2024 - Feb 2026		Principal Electrical Engineer at Capgemini North America Seattle, WA, USA
Apr 2016 - Jan 2024		Senior Electrical Engineering Tech Lead at Synapse Product Development Seattle, WA, USA A Capgemini Company Innovation and cutting-edge product development for Fortune 500 companies Project EE team leadership responsibilities provide leadership, guidance and mentoring to project EE team represent EE team to PM, client as well as external partners and vendors work with PM, discipline tech leads and client on requirements, product definition, system architecture and integration formulate test requirements, plan and approach execute on project development plan, performing as individual contributor Delivered a chip-down i.MX8M Application Processor Platform high-speed digital connectivity (USB3, HDMI, DSI, CSI-2, M.2 Key E slot, etc.) numerous expansion slots for different product configuration options served as a super-set baseline for jump-starting product development, reducing time-to-market Delivered a high-bandwidth FPGA-based data aggregation system data receiption from multiple, multi-lane 800 Mbps LVDS busses data buffering in external DDR3 memory channel aggregation and starvation-free arbitration data transmission on two USB 3 links, keeping them close to saturation Delivered a low-power, BLE-connected, overmolded wearable achieved battery life of 1 week for average use-cases using a 40 mAh Lipo battery Alpha-build and pre-production support in Asia rigorous design testing and failure analysis
Jul 2013 - Dec 2015		Head of Hardware Engineering at Native Instruments North America, Inc. Los Angeles, CA, USA Management of a cross-functional Hardware Development Team Team included EE, Layout, ME, and Lab Technician resources Used selected Agile methods for day-to-day operations weekly team planning using user stories, effort estimations and 'Scrumban' board daily Scrums for transparency, road-block identification and risk management demos and retrospectives at selected intervals and milestones Team composition, individual growth and budget planning Hiring process (candidate profile, pre-screening, interviews, final selection with team) Authored internal technology white papers for strategy discussion and evaluation Analysis of cost structure, identification of cost-down opportunities and methods Successfully shipped Traktor Kontrol S8 and Traktor Kontrol D2 Hardware architecture and verification of assumptions Definition of intra-board communication schemes and protocols Schematic design and entry using Altium Designer Firmware architecture and implementation on low-cost Microcontroller Strategy definition for test automation during development stages using LabVIEW Regulatory testing and hands-on debugging (EMI, ESD) Driving towards project milestones in close co-operation with Program Manager Finished goods BOM, cost estimations and cost management Close co-operation with Asian CMs during development, pre- and mass production ECN creation, review and approval Maintenance of production-floor Audio Test Tool using LabVIEW
Nov 2011 - Jun 2013		Team Lead Advanced Development at PreSonus Audio Electronics, Inc. Los Angeles, CA, USA Development of a backplane digital audio communication card Architecture and system integration definition Schematic design and entry using PADS Prototyping, bring-up and debug Development of a Graphic Equalizer FPGA module 31-band, 16 channel fixed-point design with 4-sample parameter smoothing Architecture definition, up-front evaluation of performance and resource utilization Implementation of core in VHDL Implementation of self-checking testbench in Verilog Simulation and functional verification using Actel Active-HDL Simulator Real-time audio quality verification using AudioPrecision measurements on hardware Prototyping of a PCI Express Soundcard FPGA system Specification of system operation targeting Thunderbolt applications FPGA architecture based on MicroBlaze System-on-Chip Development of AXI and AXI-Lite FPGA cores Development of MicroBlaze firmware Prototyping using Xilinx SP605 development board Improved FPGA development and verification workflow Selected Aldec Active-HDL toolchain Introduced usage of Assertions Utilized Property Specification Language (PSL) in separate verification units Improved availability and accuracy of cost estimates in early development stages selected Eng-DB-2 Handling of part and assembly quotes from CMs
Oct 2009 - Nov 2011		Digital Hardware Engineer at Avid Technology, Inc. Los Angeles, CA, USA
Jul 2008 - Oct 2009		Software Design Engineer at Avid Technology, Inc. Vancouver, B.C., Canada Product development for professional audio, video and multi-media industry Design, implementation and verification of FPGA systems Implementation in both VHDL and Verilog Verification using Modelsim, Icarus Verilog and C++ behavioral models Implementation of audio processing and protocol modules multi-channel, 31-band GEQ core using extended floating-point precision multi-rate, multi-link I2S, I8S and TDM Receive / Transmit modules I2S sample rate integer-factor up- and downscaler cores UI Controller cores: LED Matrix PWM, Local Bus, Register Set Research and analysis of emerging digital audio technologies Active participation in IEEE and Industry Alliance working groups IEEE 1722-2001 and IEEE P1722.1 Architecture, implementation and analysis of Proof-of-Concept prototypes Creation of White Papers Design and development of Firmware and Software modules DSP Algorithm and firmware development in C, C++ and Assembler Controller firmware development in C/C++ Implementation of module unit tests
Mar 2007 - Jul 2008		Telecommunications Software Designer at SaneWave, Inc. Vancouver, B.C., Canada
Oct 2006 - Feb 2007		Hardware Engineer at SaneWave, Inc. Hamburg, Germany Contract Engineering for companies in Professional Audio Industry Development of Audio Hardware Products Schematic design and entry using PADS Layout review Prototyping and testing Firmware Development in C/C++ Design, implementation and verification of FPGA systems Implementation in VHDL and Verilog Verification using open-source GHDL and Icarus Verilog Implementation of various protocol modules (I2S, I8S, TDIF, SPI)
		Development of Intellectual Property Digital Audio Streaming System-on-Chip based on Gigabit Ethernet System-on-Chip design leveraging OpenRISC soft-processor
Jan 2006 - Oct 2006		Hardware Development Engineer at Avionic Design Development GmbH Hamburg, Germany Product Development and in-house Manufacturing for Aviation and Entertainment Industry Development of Embedded Systems Schematic design, entry and Layout Prototype bring-up and testing Implementation of protocols for data transmission and communication Firmware development in C/C++ Design, implementation and verification of FPGA systems Design implementation in VHDL Design verification with GHDL Development of a Video Scaler using a 2-dimensional Cubic Spline digital filter Analysis of in-production Microprocessor Systems for cost and performance optimization

Education

2002 - 2006		MSEE (Dipl. Ing. Elektrotechnik / Nachrichtentechnik) Graduated from Technical University Hamburg-Harburg Majored in Telecommunications and Digital Transmitting Techniques
1998 - 2002		BSEE (Cand. Ing. Elektrotechnik) Graduated from Technical University Hamburg-Harburg

Other Experience and Qualifications

Firm basis of Agile methods, experience in application to waterfall hardware development.
Active co-developer of open-source engineering database Eng-DB-2.
Co-Author of Patent US 20120143360 A1.
Named Contributor to AVB Ethernet standards IEEE 1722-2011 and IEEE 1722.1-2013.
Authorized to work for any employer in the US or Europe.
Able to do business in both English and German.

Portfolio: JoernHenneberg_Portfolio_web.pdf
References upon request.